ENOSYS
IntEgrated ModelliNg and Synthesis tOol flow for Embedded SYStems Design (ENOSYS)
| Coordinatore | SOFTEAM
Organization address
address: Avenue Victor Hugo 21 contact info |
| Nazionalità Coordinatore | France [FR] |
| Totale costo | 3˙971˙409 € |
| EC contributo | 2˙595˙657 € |
| Programma | FP7-ICT
Specific Programme "Cooperation": Information and communication technologies |
| Code Call | FP7-ICT-2009-4 |
| Funding Scheme | CP |
| Anno di inizio | 2010 |
| Periodo (anno-mese-giorno) | 2010-01-01 - 2012-12-31 |
Partecipanti
| # | ||||
|---|---|---|---|---|
| 1 |
SOFTEAM
Organization address
address: Avenue Victor Hugo 21 contact info |
FR (PARIS) | coordinator | 0.00 |
| 2 |
Axilica Limited
Organization address
address: Elizabeth House, York Rd 39 contact info |
UK (London) | participant | 0.00 |
| 3 |
INTRACOM SA TELECOM SOLUTIONS
Organization address
address: NEW ROAD PEANIA MARKOPOULO 19 7KM contact info |
EL (PEANIA) | participant | 0.00 |
| 4 |
LOUGHBOROUGH UNIVERSITY
Organization address
address: Ashby Road contact info |
UK (LOUGHBOROUGH) | participant | 0.00 |
| 5 |
THALES COMMUNICATIONS & SECURITY SAS
Organization address
address: AVENUE DES LOUVRESSES 4 contact info |
FR (GENNEVILLIERS) | participant | 0.00 |
| 6 |
UNIVERSITY OF PELOPONNESE
Organization address
address: STAVROU 28 KAI KARYOTAKI 28 contact info |
EL (TRIPOLI) | participant | 0.00 |
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Obiettivo del progetto (Objective)
The main objectives of the ENOSYS project are to shorten time to market and reduce design costs in the development of new electronic products. This is of prime importance to European companies seeking to increase their share of the competitive consumer electronics market, where the flexibility to move quickly to add distinguishing features, such as faster operation, lower power consumption or miniaturization, is paramount. ENOSYS intends to achieve this by allowing designers to work at a high level of abstraction and removing the need to concentrate on the time-consuming details of the design.nENOSYS proposes a seamless tool flow for embedded systems modeling and synthesis and addresses the integration and enhancement of existing tools from European SME vendors (SOFTEAM and Axilica) to build a common extendable design environment. This will be delivered through: (a) the development of approaches for embedded system specification on different abstraction layers; (b) the development of efficient techniques for the exploration of the hardware/software design space and (c) the automatic synthesis of efficient descriptions for both hardware (synthesizable HDL) and embedded software (C/C\) components of the targeted system from models based on UML MARTE profile. To evaluate and to bring the proposed concepts to industrial application ENOSYS performs two complementary case studies (INTRACOM Telecom and THALES) covering wireless and/or multimedia application representing the future system complexity. Loughborough University and University of Peloponnese will deliver important new enhancements to improve performance and general applicability.nThrough active participation in the OMG standardization activities, results will be exploited both during the project and will persist long after completion. The partners will have the opportunity to transfer their actual design needs, stemming from real world cases studies in highly demanding application areas to emerging standards.