POLYSYS
POLYSYS: Direct 100G connectivity with optoelectronic POLYmer-InP integration for data center SYstems
| Coordinatore | INSTITUTE OF COMMUNICATION AND COMPUTER SYSTEMS
Organization address
address: Iroon Polytechniou 9 contact info |
| Nazionalità Coordinatore | Greece [EL] |
| Totale costo | 3˙919˙341 € |
| EC contributo | 2˙560˙000 € |
| Programma | FP7-ICT
Specific Programme "Cooperation": Information and communication technologies |
| Code Call | FP7-ICT-2009-5 |
| Funding Scheme | CP |
| Anno di inizio | 2010 |
| Periodo (anno-mese-giorno) | 2010-10-01 - 2014-01-31 |
Partecipanti
| # | ||||
|---|---|---|---|---|
| 1 |
INSTITUTE OF COMMUNICATION AND COMPUTER SYSTEMS
Organization address
address: Iroon Polytechniou 9 contact info |
EL (Zografou) | coordinator | 0.00 |
| 2 |
FRAUNHOFER-GESELLSCHAFT ZUR FOERDERUNG DER ANGEWANDTEN FORSCHUNG E.V
Organization address
address: Hansastrasse contact info |
DE (MUNCHEN) | participant | 0.00 |
| 3 | GIGOPTIX-HELIX AG | CH | participant | 0.00 |
| 4 |
III V LAB
Organization address
address: ROUTE DE NOZAY contact info |
FR (MARCOUSSIS) | participant | 0.00 |
| 5 |
Linkra S.R.L.
Organization address
address: Via Guido Rossa contact info |
IT (Cornate d'Adda) | participant | 0.00 |
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Obiettivo del progetto (Objective)
Optical connectivity in data centers relies on 10Gb/s parallel optics that raise scalability and energy consumption issues. Efforts towards advanced modulation formats pose severe system complexity. The upgrade to 100 Gb/s to resolve the bandwidth bottleneck and increase the throughput of optical interconnect backplanes requires a disruptive yet straightforward solution. POLYSYS aims to provide this solution and realize 100Gb/s serial connectivity for rack-to-rack and chip-to-chip interconnects. POLYSYS will use electro-optic polymer as an integration platform where 100Gb/s modulators will be integrated monolithically, whereas InP lasers, detectors and electronics will be integrated hybridly. The InP-to-polymer integration technique will enable 95% coupling efficiency without using lenses and bulk optics. POLYSYS will fabricate the first serial 100Gb/s and 4x100Gb/s transmitters integrated with <1W-consuming electronic driver ICs, achieving 10 times higher line rates than mainstream 10 Gb/s VCSEL or silicon-based commercial products. POLYSYS will furthermore integrate 4x100Gb/s optoelectronic receivers monolithically in InP. The receivers will exhibit a high conversion gain to enable direct connectivity without optical amplifiers. The electronics will be integrated in arrays and the DEMUX circuit will demonstrate record low sensitivity. POLYSYS will demonstrate 4x100Gb/s direct data interconnection, increasing by 4 times the total throughput and reducing at least by a factor of 2 the required Energy/bit with respect to commercially available products. By demonstrating optical demultiplexing based on polymer, POLYSYS will show that the energy/bit can be further decreased by a factor of 5. Finally, POLYSYS will demonstrate serial 100Gb/s chip-to-chip interconnection by integrating transmitter and receiver at both ends of a polymer waveguide chip. As such POLYSYS will show compatibility with polymer backplanes and provide the technology for a tenfold capacity upgrade.