PROBE-BURN

Probe burn phenomena: Predictive modeling and characterization for high power wafer test applications

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 Obiettivo del progetto (Objective)

'As the probe size shrinks due to finer device pitches, its current carrying capability (CCC) is also reduced, conflicting with the future wafer test requirements for power delivery. Probe burn can result in damage to probe-card or pad of wafer tested, causing significant semiconductor wafer yield loss. The approach in the test industry has been mostly experimental for baseline data for determining this key parameter-CCC of probes on probe cards. Often, the CCC of a probe calculated empirically, does not agree well with measurements for dc and especially pulsed current applications. Accurate analytical models are needed for predicting probe CCC under both dc or pulsed current test loading for probes under compression. The main goal of the proposed research is to establish fundamental understanding of the probe burn phenomena through development of accurate models of probe current carrying capacity and verification of numerical and analytical models by data collected using a precise experimental measurement methodology. We will develop advanced analytical models representing electro-thermal characteristic of contacting probe and its environment by using advanced meshing techniques to perform simulations for any probe geometry. Time dependent algorithms to predict pulsed current loading will be included in the predictive tool. There will be special focus on cantilever or MEMS-type probes where the current restriction and probe burn happens on the probe tips. The software tool developed will be help users to optimize probe design and predict CCC limits accurately, thus prevent provide probe burn failures before wafer test. Another objective is to develop a cost-effective current limiter tool via thermistors mounted on a printed-circuit-board for advanced probe card technologies. This will be demonstrated using probe-cards for specific device power requirements.'

Introduzione (Teaser)

The semiconductor industry relies on wafer tests to ensure that electrical connections are functional but the tests are damaging test probes in the process. Novel models and sensors developed with EU funding should meet the challenge.

Descrizione progetto (Article)

As devices and thus test probe tips shrink in size, the current carrying capability (CCC) of the probe is also reduced. At the same time, the maximum current required to test some components is increasing. Taken together, the risk of current-related probe tip damage or burn is increasing and that, in turn, can damage the wafer itself.

Scientists are developing models of CCC phenomena to enable better probe designs for high-power wafer tests with EU-funding of the project PROBE-BURN. They are also investigating the potential of a current control tool for advanced probe technologies exploiting a thermistor to minimise current flow before damage occurs.

During the first project period, scientists successfully developed a numerical method that can compute temperature distribution along a probe body. Researchers started with an experimental determination of CCC based on the relationship between mechanical degradation and CCC. They chose a permanent reduction in force at the probe as an experimental measure of CCC and collected data from numerous samples. Using computational mechanical methods and the phenomenon of Joule heating produced by a current flowing through a resistance, researchers then developed a numerical determination of CCC. They computed the temperature distribution along the probe body. If the temperature at any point exceeded the melting point of the body material, the associated current was defined as the CCC.

Experimental and numerical results were in excellent agreement, confirming the validity of the numerical methods to determine CCC. The team is fine-tuning the model and in the process of acquiring commercial thermistors to develop the current control tool in the second project phase.

Probe burns are an increasingly prevalent problem associated with wafer tests. Novel tools to both design and monitor probe tips during wafer tests should significantly reduce the impact of this pressing problem. This should result in significant savings for the semiconductor industry in terms of money, time and resources.