RAVEN10
DESIGN OF EXTREMELY ENERGY-EFFICIENT MULTI-CORE PROCESSOR IN NANOSCALE CMOS FOR MEDIA PROCESSING IN PORTABLE DEVICES
| Coordinatore | UNIVERSIDAD POLITECNICA DE MADRID
Organization address
address: Calle Ramiro de Maeztu 7 contact info |
| Nazionalità Coordinatore | Spain [ES] |
| Totale costo | 230˙027 € |
| EC contributo | 230˙027 € |
| Programma | FP7-PEOPLE
Specific programme "People" implementing the Seventh Framework Programme of the European Community for research, technological development and demonstration activities (2007 to 2013) |
| Code Call | FP7-PEOPLE-2010-IOF |
| Funding Scheme | MC-IOF |
| Anno di inizio | 2011 |
| Periodo (anno-mese-giorno) | 2011-07-01 - 2014-06-30 |
Partecipanti
| # | ||||
|---|---|---|---|---|
| 1 |
UNIVERSIDAD POLITECNICA DE MADRID
Organization address
address: Calle Ramiro de Maeztu 7 contact info |
ES (MADRID) | coordinator | 230˙027.20 |
Mappa
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Obiettivo del progetto (Objective)
'Many of the future applications that will drive the need for greater performance are naturally highly parallel and process massive data sets, where individual point results are of less interest than aggregate statistics or behavior. Examples include statistical machine learning, rich human-machine interfaces, and physical modeling for games and virtual worlds. In this project, the goal is to develop new highly parallel many-core architectures that exploit the attributes of these parallel, error-tolerant applications to tolerate variability in a projected future 11nm process at very low supply voltages and hence attain large gains in energy efficiency. An integrated cross-disciplinary research program is proposed cutting across software, architecture, and circuits. The architecture is named Raven (Resilient Architecture with Vector-thread ExecutioN). Each Raven core is a single vector-thread lane, with an independent control processor and a vector-thread execution engine, and hundreds of such lanes will be designed to fit in the area budget. Cores with similar characteristics will be identified through the pre-characterization phase and will be grouped to form clusters. Their delay and performance will be notified to control processor, so that it can perform dynamic scheduling of tasks to cores with a goal of achieving extreme energy efficiency. Additionally, hardware delay and performance monitors will be embedded in logic so that the process variability can be controlled through immediate dynamic reconfiguration. The greatest benefits will accrue from recognizing the optimization opportunities that the individual research ideas enable across the software/architecture/circuits stack. The applicant will not only acquire multidisciplinary training through the execution of the proposed project, but will also be guided by the experts who have gained worldwide recognition in their field and will have the opportunity to collaborate with leading electronic companies.'
Introduzione (Teaser)
Parallel processing in which multiple processors perform operations in different subsets of data is critical for many multimedia applications. A new chip architecture employing smart energy management schemes could slash energy consumption of portable devices.