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HECTOR SIGNED

HARDWARE ENABLED CRYPTO AND RANDOMNESS

Total Cost €

EC-Contrib. €

Partnership

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Outcomes and
results

HECTOR project word cloud

Explore the words cloud of the HECTOR project. It provides you a very rough idea of what is the project "HECTOR" about.

terabit attack companies bit records academia hardware latency constrained flipped power rng physically rngs experts optimal building gradual flexible flexibility time metrics designs uncloneable complementary inputs primitives combined low demonstrable industry lower integrating weak benefit countermeasures demonstrated pufs extremely algorithms cryptographic functions certification efficient quality ict mixing blocks expertise easier memory attacks pseudo fail strength ultimately physical collective publications networks randomness degradation evaluation mathematical customers gap unknown guarantees entropy cryptography single bodies ambitions efficiency security implementations heaven throughput evaluations close labs random generators secure track fly encryption generator true standardization tolerated

Project "HECTOR" data sheet

The following table provides information about the project.

Coordinator	TECHNIKON FORSCHUNGS- UND PLANUNGSGESELLSCHAFT MBH Organization address address: BURGPLATZ 3A city: VILLACH postcode: 9500 website: www.technikon.at contact info title: n.a. name: n.a. surname: n.a. function: n.a. email: n.a. telephone: n.a. fax: n.a.
Coordinator Country	Austria [AT]
Project website	https://hector-project.eu/
Total cost	4˙494˙087 €
EC max contribution	4˙494˙087 € (100%)
Programme	1. H2020-EU.2.1.1. (INDUSTRIAL LEADERSHIP - Leadership in enabling and industrial technologies - Information and Communication Technologies (ICT))
Code Call	H2020-ICT-2014-1
Funding Scheme	RIA
Starting year	2015
Duration (year-month-day)	from 2015-03-01 to 2018-02-28

Partnership

Take a look of project's partnership.

#	participants	country	role	EC contrib. [€]
1	TECHNIKON FORSCHUNGS- UND PLANUNGSGESELLSCHAFT MBH TECHNIKON FORSCHUNGS- UND PLANUNGSGESELLSCHAFT MBH Organization address address: BURGPLATZ 3A city: VILLACH postcode: 9500 website: www.technikon.at contact info title: n.a. name: n.a. surname: n.a. function: n.a. email: n.a. telephone: n.a. fax: n.a.	AT (VILLACH)	coordinator	540˙468.00
2	KATHOLIEKE UNIVERSITEIT LEUVEN KATHOLIEKE UNIVERSITEIT LEUVEN Organization address address: OUDE MARKT 13 city: LEUVEN postcode: 3000 website: www.kuleuven.be contact info title: n.a. name: n.a. surname: n.a. function: n.a. email: n.a. telephone: n.a. fax: n.a.	BE (LEUVEN)	participant	595˙500.00
3	STMICROELECTRONICS ROUSSET SAS STMICROELECTRONICS ROUSSET SAS Organization address address: AVENUE COQ ZI PEYNIER ROUSSET city: ROUSSET postcode: 13790 website: www.st.com contact info title: n.a. name: n.a. surname: n.a. function: n.a. email: n.a. telephone: n.a. fax: n.a.	FR (ROUSSET)	participant	573˙618.00
4	THALES SIX GTS FRANCE SAS THALES SIX GTS FRANCE SAS Organization address address: AVENUE DES LOUVRESSES 4 city: GENNEVILLIERS postcode: 92230 website: www.thalesgroup.com contact info title: n.a. name: n.a. surname: n.a. function: n.a. email: n.a. telephone: n.a. fax: n.a.	FR (GENNEVILLIERS)	participant	549˙375.00
5	TECHNISCHE UNIVERSITAET GRAZ TECHNISCHE UNIVERSITAET GRAZ Organization address address: RECHBAUERSTRASSE 12 city: GRAZ postcode: 8010 website: www.tugraz.at contact info title: n.a. name: n.a. surname: n.a. function: n.a. email: n.a. telephone: n.a. fax: n.a.	AT (GRAZ)	participant	518˙750.00
6	UNIVERSITE JEAN MONNET SAINT-ETIENNE UNIVERSITE JEAN MONNET SAINT-ETIENNE Organization address address: RUE TREFILERIE 10 city: SAINT ETIENNE postcode: 42023 website: www.portail.univ-st-etienne.fr contact info title: n.a. name: n.a. surname: n.a. function: n.a. email: n.a. telephone: n.a. fax: n.a.	FR (SAINT ETIENNE)	participant	489˙875.00
7	MICRONIC AS MICRONIC AS Organization address address: TREBEJOV 41 city: KYSAK postcode: 4481 website: n.a. contact info title: n.a. name: n.a. surname: n.a. function: n.a. email: n.a. telephone: n.a. fax: n.a.	SK (KYSAK)	participant	472˙000.00
8	STMICROELECTRONICS SRL STMICROELECTRONICS SRL Organization address address: VIA C.OLIVETTI 2 city: AGRATE BRIANZA postcode: 20864 website: www.st.com contact info title: n.a. name: n.a. surname: n.a. function: n.a. email: n.a. telephone: n.a. fax: n.a.	IT (AGRATE BRIANZA)	participant	413˙250.00
9	BRIGHTSIGHT BV BRIGHTSIGHT BV Organization address address: BRASSERSPLEIN 2 city: DELFT postcode: 2612 CT website: n.a. contact info title: n.a. name: n.a. surname: n.a. function: n.a. email: n.a. telephone: n.a. fax: n.a.	NL (DELFT)	participant	341˙250.00

Map

Project objective

A single flipped bit or a weak random number generator can cause secure systems to fail. The main objective of this proposal is to close the gap between the mathematical heaven of cryptographic algorithms and their efficient, secure and robust hardware implementations. It requires integrating secure cryptographic primitives such as random number generators (RNGs) and physically uncloneable functions (PUFs), together with physical attack countermeasures. Therefore we will study, design and implement RNGs and PUFs with demonstrable entropy guarantees and quality metrics. This includes on-the-fly entropy testing and physical attacks evaluations. This will enable more secure systems and easier certification. State-of-the-art cryptography and countermeasures can fail due to low-entropy random numbers. The unknown is ‘how much’ they will fail and how much entropy degradation can be tolerated (due to attacks or RNG designs mixing true and pseudo randomness). Our objective is to study the strength and gradual security degradation when using lower entropy random numbers. This will enable more optimal and secure implementations. These objectives have to be combined with hardware efficiency and flexibility. This means addressing the extremely low-cost and low-power requirements of constrained embedded devices, low-latency of real-time memory encryption, or high throughput of future terabit networks. Ultimately, we target security building blocks that are flexible, hardware-friendly, efficient, and robust against physical attacks, and which will be demonstrated on European relevant use cases. We bring together experts from industry, academia and evaluation labs with collective ambitions, potential and track records and with complementary expertise, dissemination and impact potential. Results will not only benefit the companies involved and their customers, but also the broader ICT through publications and inputs to standardization and certification bodies.

Deliverables

List of deliverables.
Report on Selected TRNG and PUF Principles	Documents, reports	2019-04-18 14:11:29
Report on Attacks	Documents, reports	2019-04-18 14:01:26
Demonstrator Specification	Documents, reports	2019-04-18 14:01:28
Project Quality Plan	Other	2019-04-18 14:01:23
Demonstrator Security Evaluation	Documents, reports	2019-04-18 14:01:29
Report on the Efficient Implementations of Crypto Algorithms and Building Blocks and on Cost and Benefits of Countermeasures Against Physical Attacks	Documents, reports	2019-04-18 14:01:24
Data Management Plan (DMP)	Documents, reports	2019-04-18 14:01:30
Internal and External IT Communication Infrastructure and Project Website	Websites, patent fillings, videos etc.	2019-04-18 14:01:29
Risk Assessment Plan	Documents, reports	2019-04-18 14:01:28
Final Report on Data Management	Open Research Data Pilot	2019-04-18 14:11:21
Report on the Security Evaluation of Cryptographic Algorithms and Countermeasures when non Ideal Hardware Building Blocks are Used	Documents, reports	2019-04-18 14:01:29
Demonstrator Platform	Demonstrators, pilots, prototypes	2019-04-18 14:01:25

Take a look to the deliverables list in detail: detailed list of HECTOR deliverables.

Publications

List of publications.
year	authors and title	journal	last update
2016	Dobraunig Christoph, Eichlseder Maria, Mendel Florian Square Attack on 7-Round Kiasu-BC published pages: , ISSN: , DOI: 10.5281/zenodo.55445	14th International Conference on Applied Cryptography and Network Security	2019-05-30
2016	Dobraunig, Christoph; Eichlseder, Maria; Korak, Thomas; Lomne, Victor; Mendel, Florian Statistical Fault Attacks on Nonce-Based Authenticated Encryption Schemes published pages: , ISSN: , DOI: 10.5281/zenodo.154485	22nd Annual International Conference on the Theory and Applications of Cryptology and Information Security (Asiacrypt2016)	2019-05-30
2018	Maria Eichlseder, Daniel Kales Clustering Related-Tweak Characteristics: Application to MANTIS-6 published pages: , ISSN: 2519-173X, DOI: 10.13154/tosc.v2018.i2.111-132	IACR Transactions on Symmetric Cryptology	2019-05-30
2016	Gruss Daniel, Maurice Clementine, Mangard Stefan Rowhammer.js: A Remote Software-Induced Fault Attack in JavaScript published pages: , ISSN: , DOI: 10.5281/zenodo.55447	13th Conference on Detection of Intrusions and Malware & Vulnerability Assessment	2019-05-30
2015	Corinna Kudler; Kathrin Assmayr; Martin Deutschmann; Nele Mentens D6.2 - Project Quality Plan published pages: , ISSN: , DOI: 10.5281/zenodo.801213	62	2019-05-30
2016	Rozic Vladimir, Yang Bohan, Dehaene Wim, Verbaudwhede Ingrid Iterating Von Neumannâ€™s Post-Processing under Hardware Constraints published pages: , ISSN: , DOI: 10.5281/zenodo.55456	IEEE Int. Symposium on Hardware-Oriented Security and Trust	2019-05-30
2016	Yang Bohan, Rozic Vladimir, Mentens Nele, Dehaene Wim, Verbaudwhede Ingrid TOTAL: TRNG On-the-fly Testing for Attack detection using Lightweight hardware published pages: , ISSN: , DOI: 10.5281/zenodo.55455	Design, Automation & Test in Europe Conference & Exhibition	2019-05-30
2016	Rozic Vladimir, Yang Bohan, Mentens Nele, Verbauwhede Ingrid Canary Numbers: Design for Light-weight Online Testability of True Random Number Generators published pages: , ISSN: , DOI: 10.5281/zenodo.56625	Random Bit Generation Workshop 2016	2019-05-30
2015	Bochard, Nathalie; Marchand, Cedric; Petura, Oto; Bossuet, Lilian; Fischer, Viktor Evariste III: A new multi-FPGA system for fair benchmarking of hardware dependent cryptographic primitives published pages: , ISSN: , DOI: 10.5281/zenodo.61294	Workshop on Cryptographic Hardware and Embedded Systems	2019-05-30
2016	Lipp, Moritz; Gruss, Daniel; Spreitzer, Raphael; Maurice, ClÃ©mentine; Mangard, Stefan ARMageddon: Cache Attacks on Mobile Devices published pages: , ISSN: , DOI: 10.5281/zenodo.59889	25th Annual USENIX Security Symposium	2019-05-30
2016	Delvaux Jeroen, Gu Dawu, Verbaudwhede Ingrid, Hiller Matthias, Yu Meng-Day Efficient Fuzzy Extraction of PUF-Induced Secrets: Theory and Applications published pages: , ISSN: , DOI: 10.5281/zenodo.55449	Conference on Cryptographic Hardware and Embedded Systems 2016	2019-05-30
2016	Dobraunig, Christoph; Eichlseder, Maria; Mendel, Florian Analysis of the Kupyna-256 Hash Function published pages: , ISSN: , DOI: 10.5281/zenodo.121361	ACM SIGSOFT International Symposium on the Foundations of Software Engineering	2019-05-30
2016	Gruss Daniel, Maurice Clementine, Wagner Klaus, Mangard Stefan Flush+Flush: A Fast and Stealthy Cache Attack published pages: , ISSN: , DOI: 10.5281/zenodo.55446	13th Conference on Detection of Intrusions and Malware & Vulnerability Assessment	2019-05-30
2016	Fischer, Viktor Sources of Randomness in Digital Devices and their Testability published pages: , ISSN: , DOI: 10.5281/zenodo.58127	Random Bit Generation Workshop 2016	2019-05-30
2015	Gruss Daniel, Spreitzer Raphael, Mangard Stefan Cache Template Attacks: Automating Attacks on Inclusive Last-Level Caches published pages: , ISSN: , DOI: 10.5281/zenodo.55454	24th USENIX Security Symposium 2015	2019-05-30
2017	Hannes Gross; Stefan Mangard Reconciling d+1 Masking in Hardware and Software published pages: , ISSN: , DOI: 10.5281/zenodo.897934	2	2019-04-18
2016	Jeroen Delvaux; Dawu Gu; Ingrid Verbauwhede Upper Bounds on The Min-Entropy of RO Sum, Arbiter, Feed-Forward Arbiter, and S-ArbRO PUFs published pages: , ISSN: , DOI: 10.5281/zenodo.375498	3	2019-04-18
2017	Kai-Hsin Chuang; Erik Bury; Robin Degraeve; Ben Kaczer; Guido Groeseneken; Ingrid Verbauwhede; Dimitri Linten Physically Unclonable Function Using CMOS Breakdown Position published pages: , ISSN: , DOI: 10.5281/zenodo.571735	2	2019-04-18
2018	Eichlseder, Maria Differential Cryptanalysis of Symmetric Primitives published pages: , ISSN: , DOI: 10.5281/zenodo.1288325	1	2019-04-18
2016	Daniel Gruss; ClÃ©mentine Maurice; Victor van der Veen; Herbert Bos; Kaveh Razavi; Cristiano Giuffrida; Yanick Fratantonio; Martina Lindorfer; Giovanni Vigna Drammer: Deterministic Rowhammer Attacks on Mobile Platforms published pages: , ISSN: , DOI: 10.5281/zenodo.375506	4	2019-04-18
2016	Dobraunig, Christoph; Eichlseder, Maria; Korak, Thomas; Lomne, Victor; Mendel, Florian Statistical Fault Attacks on Nonce-Based Authenticated Encryption Schemes published pages: , ISSN: , DOI: 10.5281/zenodo.154487	4	2019-04-18
2018	Cedric Marchand, Lilian Bossuet, Ugo Mureddu, Nathalie Bochard, Abdelkarim Cherkaoui, Viktor Fischer Implementation and Characterization of a Physical Unclonable Function for IoT: A Case Study With the TERO-PUF published pages: 97-109, ISSN: 0278-0070, DOI: 10.1109/TCAD.2017.2702607	IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 37/1	2019-04-18
2017	Christoph Dobraunig; Maria Eichlseder; Stefan Mangard; Florian Mendel; Thomas Unterluggauer ISAP -- Towards Side-Channel Secure Authenticated Encryption published pages: , ISSN: , DOI: 10.13154/tosc.v2017.i1.80-105	2519-173X 3	2019-04-18
2017	Christoph Dobraunig; Maria Eichlseder; Daniel Kales; Florian Mendel Practical Key-Recovery Attack on MANTIS-5 published pages: , ISSN: , DOI: 10.5281/zenodo.574265	2519-173X 3	2019-04-18
2016	Cao, Yang; Rozic, Vladimir; Yang, Bohan; Balasch, Josep; Verbauwhede, Ingrid Exploring active manipulation attacks on the TERO random number generator published pages: , ISSN: , DOI: 10.5281/zenodo.154591	4	2019-04-18
2017	Hannes Gross; Stefan Mangard; Thomas Korak An Efficient Side-Channel Protected AES Implementation with Arbitrary Protection Order published pages: , ISSN: , DOI: 10.5281/zenodo.574261	3	2019-04-18
2017	Vladimir Rozic; Bohan Yang; Jo Vliegen; Nele Mentens; Ingrid Verbauwhede The Monte Carlo PUF published pages: , ISSN: , DOI: 10.5281/zenodo.897887	2	2019-04-18
2015	Corinna KUDLER; Martin DEUTSCHMANN; Mario MÃœNZER; Felix STORNIG; Thomas KORAK D5.1 - Internal and External IT Communication Infrastructure and Project Website published pages: , ISSN: , DOI: 10.5281/zenodo.801166	16	2019-04-18
2016	Daniel Gruss; ClÃ©mentine Maurice; Moritz Lipp; Stefan Mangard; Anders Fogh Prefetch Side-Channel Attacks: Bypassing SMAP and Kernel ASLR published pages: , ISSN: , DOI: 10.5281/zenodo.375513	4	2019-04-18
2016	Guido Bertoni; Marco Martinoli A Methodology for the Characterization of Leakages in Combinatorial Logic published pages: , ISSN: , DOI: 10.5281/zenodo.571605	3	2019-04-18
2017	Colombier, Brice; Mureddu, Ugo; Laban, Marek; Petura, Oto; Bossuet, Lilian; Fischer, Viktor Complete activation scheme for IP design protection published pages: , ISSN: , DOI: 10.5281/zenodo.574260	https://hal-ujm.archives-ouvertes.fr/ujm-01575569 2	2019-04-18
2016	Mureddu, Ugo; Bossuet, Lilian; Fischer, Viktor A comparison of PUF cores suitable for FPGA devices published pages: , ISSN: , DOI: 10.5281/zenodo.1287571	Conference on trustworthy Manufacturing and Utilization of Secure Devices (TRUDEVICE), 2016, Barcelone, Spain. 2016 4	2019-04-18
2017	Elia Bisi, Filippo Melzani, Vittorio Zaccaria Symbolic Analysis of Higher-Order Side Channel Countermeasures published pages: 1099-1105, ISSN: 0018-9340, DOI: 10.1109/TC.2016.2635650	IEEE Transactions on Computers 66/6	2019-04-18
2017	Brice Colombier, Lilian Bossuet, Viktor Fischer, David Hely Key Reconciliation Protocols for Error Correction of Silicon PUF Responses published pages: 1988-2002, ISSN: 1556-6013, DOI: 10.1109/TIFS.2017.2689726	IEEE Transactions on Information Forensics and Security 12/8	2019-04-18
2016	Marek Laban; Milos Drutarovsky; Viktor Fischer; Michal Varchola Platform for Testing and Evaluation of PUF and TRNG Implementations in FPGAs published pages: , ISSN: , DOI: 10.5281/zenodo.163283	4	2019-04-18
2018	Madau, Maxime; Agoyan, Michel; Balasch, Josep; Grujic, Milos; Haddad, Patrick; Maurine, Philippe; Rozic, Vladimir; Singelee, Dave; Yang, Bohan; Verbauwhede, Ingrid The impact of pulsed Electromagnetic Fault Injection on true random number generators published pages: , ISSN: , DOI: 10.5281/zenodo.1434074	1	2019-04-18
2017	Bohan Yang; Vladimir Rozic; Milos Grujic; Nele Mentens; Ingrid Verbauwhede On-chip jitter measurement for true random number generators published pages: , ISSN: , DOI: 10.5281/zenodo.897896	2	2019-04-18
2018	Hannes Gross, Stefan Mangard A unified masking approach published pages: 109-124, ISSN: 2190-8508, DOI: 10.1007/s13389-018-0184-y	Journal of Cryptographic Engineering 8/2	2019-04-18
2018	Florent Bernard, Patrick Haddad, Viktor Fischer, Jean Nicolai From Physical to Stochastic Modeling of a TERO-Based TRNG published pages: , ISSN: 0933-2790, DOI: 10.1007/s00145-018-9291-2	Journal of Cryptology	2019-04-18
2018	Petura, Oto; Mureddu, Ugo; Bochard, Nathalie; Fischer, Viktor; Bossuet, Lilian Evaluation of AIS-20/31 compliant TRNG cores implemented on FPGAs published pages: , ISSN: , DOI: 10.5281/zenodo.1287567	https://hal.archives-ouvertes.fr/hal-01382990 1	2019-04-18
2017	Milos Grujic, Vladimir Rozic, Bohan Yang, Ingrid Verbauwhede Lightweight Prediction-Based Tests for On-Line Min-Entropy Estimation published pages: 45-48, ISSN: 1943-0663, DOI: 10.1109/LES.2017.2687082	IEEE Embedded Systems Letters 9/2	2019-04-18
2016	Martin DEUTSCHMANN; Sandra LATTACHER; Jeroen DELVAUX; Vladimir ROZIC; Bohan YANG; Dave SINGELEE; Lilian BOSSUET; Viktor FISCHER; Ugo MUREDDU; Oto PETURA; Alexandre ANZALA YAMAJAKO; Bernard KASSER; Gerard BATTUM D2.1 - Report on Selected TRNG and PUF Principles published pages: , ISSN: , DOI: 10.5281/zenodo.801083	10	2019-04-18
2018	Petura , Oto; Laban , Marek; Noumon Allini , Elie ,; Fischer , Viktor Two Methods of the Clock Jitter Measurement Aimed at Embedded TRNG Testing published pages: , ISSN: , DOI: 10.5281/zenodo.1284209	Trustworthy Manufacturing and Utilization of Secure Devices (TRUDEVICE 2018) 1	2019-04-18
2018	Balasch, Josep; Bernard, Florent; Fischer, Viktor; Grujic, Milos; Laban, Marek; Petura, Oto; Rozic, Vladimir; Van Battum, Gerard; Verbauwhede, Ingrid; Wakker, Marnix; Yang, Bohan Design and Testing Methodologies for True Random Number Generators Towards Industry Certification published pages: , ISSN: , DOI: 10.5281/zenodo.1289440	2	2019-04-18
2018	Raphael Spreitzer, Veelasha Moonsamy, Thomas Korak, Stefan Mangard Systematic Classification of Side-Channel Attacks: A Case Study for Mobile Devices published pages: 465-488, ISSN: 1553-877X, DOI: 10.1109/COMST.2017.2779824	IEEE Communications Surveys & Tutorials 20/1	2019-04-18
2017	Jeroen Delvaux Security Analysis of PUF-Based Key Generation and Entity Authentication published pages: , ISSN: , DOI: 10.5281/zenodo.897914	2	2019-04-18
2017	Oscar Reparaz; Benedikt Gierlichs; Ingrid Verbauwhede Fast Leakage Assessment published pages: , ISSN: , DOI: 10.5281/zenodo.897902	2	2019-04-18
2018	Allini, Elie Noumon; SkÃ³rski, Maciej; Petura, Oto; Bernard, Florent; Laban, Marek; Fischer, Viktor Evaluation and monitoring of free running oscillators serving as source of randomness published pages: , ISSN: , DOI: 10.5281/zenodo.1443138	1	2019-04-18
2018	Zaccaria, Vittorio; Melzani, Filippo; Bertoni, Guido Spectral features of higher-order side-channel countermeasures published pages: , ISSN: 0018-9340, DOI: 10.5281/zenodo.1134753	IEEE Transactions on Computers 1	2019-04-18
2018	Yang, Bohan; Rozic, Vladimir; Grujic, Milos; Mentens, Nele; Verbauwhede, Ingrid ES-TRNG: A High-throughput, Low-area True Random Number Generator based on Edge Sampling published pages: , ISSN: , DOI: 10.5281/zenodo.1434083	1	2019-04-18
2015	Martin Deutschmann; Corinna Kudler; Sandra Lattacher; Dave Singelee; Ingrid Verbauwhede; Viktor Fischer; Alexandre Anzala Yamayako; Bernard Kasser; Guido Bertoni; Michal Varchola; Gerard Battum D5.2 - Data Management Plan (DMP) published pages: , ISSN: , DOI: 10.5281/zenodo.801182	2	2019-03-11
2016	Sandra Lattacher; Martin Deutschmann; Marion Buchacher; Sandra Moschitz; Jan Seda; Dave Singelee; Viktor Fischer; Bernard Kasser D6.1 - Risk Assessment Plan published pages: , ISSN: , DOI: 10.5281/zenodo.801200	2	2019-03-11
2016	Ashur, Tomer; Liu, Yunwen Rotational Cryptanalysis in the Presence of Constants published pages: , ISSN: 2519-173X, DOI: 10.13154/tosc.v2016.i1.57-70	IACR Transactions on Symmetric Cryptology 1	2019-03-11
2017	Christoph Dobraunig; Maria Eichlseder; Florian Mendel Cryptanalysis of Simpira v1 published pages: , ISSN: , DOI: 10.5281/zenodo.375528	1	2019-03-11

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