SQWIRE

Silicon Quantum Wire Transistors

Coordinatore	UNIVERSITY COLLEGE CORK, NATIONAL UNIVERSITY OF IRELAND, CORK    more  Organization address address: Lee Maltings, Prospect Row city: Cork postcode: N/A contact info Titolo: Mr. Nome: Conor Cognome: Delaney Email: send email Telefono: +353 21 490 4263 Fax: +353 21 4904058
Nazionalità Coordinatore	Ireland [IE]
Totale costo	4˙326˙034 €
EC contributo	3˙150˙000 €
Programma	FP7-ICT Specific Programme "Cooperation": Information and communication technologies
Code Call	FP7-ICT-2009-5
Funding Scheme	CP
Anno di inizio	2010
Periodo (anno-mese-giorno)	2010-09-01   -   2013-08-31

 Partecipanti

#	participant	country	role	EC contrib. [€]
1	UNIVERSITY COLLEGE CORK, NATIONAL UNIVERSITY OF IRELAND, CORK  Organization address address: Lee Maltings, Prospect Row city: Cork postcode: N/A contact info Titolo: Mr. Nome: Conor Cognome: Delaney Email: send email Telefono: +353 21 490 4263 Fax: +353 21 4904058	IE (Cork)	coordinator	0.00
2	CENTRE NATIONAL DE LA RECHERCHE SCIENTIFIQUE  Organization address address: Rue Michel -Ange city: PARIS postcode: 75794 contact info Nome: N/A Cognome: N/A Email: send email Telefono: +00 0 000000	FR (PARIS)	participant	0.00
3	COMMISSARIAT A L ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES  Organization address address: RUE LEBLANC city: PARIS 15 postcode: 75015 contact info Titolo: Ms. Nome: Marie-Laure Cognome: Page Email: send email Telefono: +33 4 38782396 Fax: +33 4 38785183	FR (PARIS 15)	participant	0.00
4	INSTITUT POLYTECHNIQUE DE GRENOBLE  Organization address address: AVENUE FELIX VIALLET city: GRENOBLE CEDEX 1 postcode: 38031 contact info Titolo: Ms. Nome: Valerie Cognome: Miscioscia Email: send email Telefono: 33456529505 Fax: 33456529501	FR (GRENOBLE CEDEX 1)	participant	0.00
5	INTEL PERFORMANCE LEARNING SOLUTIONS LIMITED  Organization address address: Collinstown Industrial Park city: LEIXLIP, CO KILDARE postcode: . contact info Titolo: Mr. Nome: Bernard Cognome: Capraro Email: send email Telefono: +353 1 606 4228 Fax: +353 1 606 4210	IE (LEIXLIP, CO KILDARE)	participant	0.00
6	INTERUNIVERSITAIR MICRO-ELECTRONICA CENTRUM VZW  Organization address address: Kapeldreef city: LEUVEN postcode: 3001 contact info Titolo: Ms. Nome: Christine Cognome: Van Houtven Email: send email Telefono: 3216281613 Fax: 3216281812	BE (LEUVEN)	participant	0.00
7	MAGWEL NV  Organization address address: MARTELARENPLEIN city: LEUVEN postcode: 3000 contact info Titolo: Mr. Nome: Bart Cognome: De Smedt Email: send email Telefono: +32 16 46 86 88 Fax: +32 16 46 86 89	BE (LEUVEN)	participant	0.00
8	S.O.I.TEC SILICON ON INSULATOR TECHNOLOGIES SA  Organization address address: CHEMIN DES FRANQUES - PARC TECHNOLOGIQUE DES FONTAINES city: BERNIN postcode: 38190 contact info Titolo: Dr. Nome: Nelly Cognome: Kernevez Email: send email Telefono: +33 4 76 92 96 23 Fax: +33 4 76 92 94 31	FR (BERNIN)	participant	0.00
9	UNIVERSITAT ROVIRA I VIRGILI  Organization address address: CARRER DE L'ESCORXADOR city: TARRAGONA postcode: 43003 contact info Titolo: Prof. Nome: Rosa Cognome: Solà Alberich Email: send email Telefono: +34 977559522 Fax: +34 977558278	ES (TARRAGONA)	participant	0.00
10	UNIVERSITE JOSEPH FOURIER GRENOBLE 1  Organization address address: Avenue Centrale, Domaine Universitaire city: GRENOBLE postcode: 38041 contact info Nome: N/A Cognome: N/A Email: send email Telefono: +00 0 000000	FR (GRENOBLE)	participant	0.00

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 Obiettivo del progetto (Objective)

The aim of the SQWIRE project is to develop a disruptive, industry-compatible CMOS technology based on novel silicon nanowire transistor structures. The co-ordinator has demonstrated both theoretically and experimentally that nanowire MOS transistors can be fabricated at wafer level using silicon-on-insulator (SOI) substrates. These novel devices have shown electrical properties that are comparable or even superior to those of regular transistors.nTwo such novel devices are the Gated Resistor (a junctionless transistor simulated, prototype fabricated and patented) and the variable-barrier tunnel transistor (VBT, simulated and patented). To obtain industrial validation, fabrication routes will be developed for these devices on novel 300 mm SOI wafers with silicon film thicknesses of only 10 nm. These routes will be underpinned by process development targeting atom-scale control of the silicon film thickness across the wafer.nDevice performance will be characterised at die-level and evaluated in a statistically meaningful manner at wafer level. The extracted parameters will serve as the basis for the development of a compact model of the Gated Resistor devices, which can be used for further circuit design and the validation of advanced numerical simulations.nThe fabrication process for the first device (Gated Resistor) is less complex and more flexible than that of regular transistors. It has the potential of increasing yield and reducing the price of integrated circuits. Furthermore, the Gated Resistor offers the promise of superior scaling to sub-22 nm dimensions compared to regular transistors. In addition, the process can easily be implemented in semiconductor materials other than silicon. The second device (Variable Barrier Transistor) is capable of providing subthreshold slopes sharper than any conventional transistor. This permits one to reduce the supply voltage of integrated circuits, and hence their energy consumption.