WADIMOS
Wavelength Division Multiplexed Photonic Layer on CMOS
| Coordinatore | INTERUNIVERSITAIR MICRO-ELECTRONICA CENTRUM VZW
Organization address
address: Kapeldreef 75 contact info |
| Nazionalità Coordinatore | Belgium [BE] |
| Sito del progetto | http://www.wadimos.eu |
| Totale costo | 3˙115˙657 € |
| EC contributo | 2˙299˙982 € |
| Programma | FP7-ICT
Specific Programme "Cooperation": Information and communication technologies |
| Code Call | FP7-ICT-2007-1 |
| Funding Scheme | CP |
| Anno di inizio | 2008 |
| Periodo (anno-mese-giorno) | 2008-01-01 - 2011-06-30 |
Partecipanti
| # | ||||
|---|---|---|---|---|
| 1 |
INTERUNIVERSITAIR MICRO-ELECTRONICA CENTRUM VZW
Organization address
address: Kapeldreef 75 contact info |
BE (Leuven) | coordinator | 0.00 |
| 2 |
CENTRE NATIONAL DE LA RECHERCHE SCIENTIFIQUE
Organization address
address: Rue Michel -Ange contact info |
FR (PARIS) | participant | 0.00 |
| 3 |
COMMISSARIAT A L ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
Organization address
address: RUE LEBLANC contact info |
FR (PARIS 15) | participant | 0.00 |
| 4 |
ECOLE CENTRALE DE LYON
Organization address
address: Avenue Guy de Collongue contact info |
FR (ECULLY) | participant | 0.00 |
| 5 |
INSTITUT NATIONAL DES SCIENCES APPLIQUEES DE LYON
Organization address
address: Avenue Albert Einstein contact info |
FR (VILLEURBANNE) | participant | 0.00 |
| 6 |
MAPPER LITHOGRAPHY B.V.
Organization address
address: COMPUTERLAAN 15 contact info |
NL (DELFT) | participant | 0.00 |
| 7 |
STMICROELECTRONICS SRL
Organization address
address: VIA C.OLIVETTI contact info |
IT (AGRATE BRIANZA) | participant | 0.00 |
| 8 |
UNIVERSITA DEGLI STUDI DI TRENTO
Organization address
address: VIA BELENZANI contact info |
IT (TRENTO) | participant | 0.00 |
Mappa
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Obiettivo del progetto (Objective)
WADIMOS proposes to develop a generic technology for the realization of complex electro-photonic integrated ICs using standard CMOS processing technologies.nThese ICs will contain a photonic interconnect layer incorporating microsource arrays and ultracompact WDM (wavelength division multiplexing) functionality based on silicon nanophotonic wire circuits, driven directly from by the CMOS electronic circuitry. The photonic interconnect layer is intended to be incorporated in between the uppermost copper layers of an electronic IC. The availability of such ICs will benefit many applications in telecom, local access, datacom, automotives, avionics and sensing, on- and off-chip interconnect. Two applications will be investigated in particular: a 100TB/s datalink for a maskless-lithography tool based on a massively parallel e-beam tool and an optical network-on-chip based on a wavelength routed network directly integrated with CMOS circuits. The latter is addressing the expected limitations imposed by future purely electrical interconnects in complex MPSoC systems. These two applications are each backed by an industrial partner and their architectural design will be studied in separate workpackages, resulting in a set of specifications for the subcomponents forming the electro-photonic IC. Based on these inputs the different subcomponents will be designed, fabricated and characterized. The most relevant subcomponent is a III-V silicon heterogeneous multi-wavelength microsource array, which will be realized fully in a CMOS-pilot line, based on a process previously developed by project partners and independently by INTEL/USCB researchers. Finally, the different subcomponents will be integrated into two demonstrators each addressing one of both applications under study.