REFLECT
Rendering FPGAs to Multi-Core Embedded Computing
| Coordinatore | HONEYWELL INTERNATIONAL SRO
Organization address
city: Brno contact info |
| Nazionalità Coordinatore | Czech Republic [CZ] |
| Totale costo | 3˙703˙578 € |
| EC contributo | 2˙719˙999 € |
| Programma | FP7-ICT
Specific Programme "Cooperation": Information and communication technologies |
| Code Call | FP7-ICT-2009-4 |
| Funding Scheme | CP |
| Anno di inizio | 2010 |
| Periodo (anno-mese-giorno) | 2010-01-01 - 2012-12-31 |
Partecipanti
| # | ||||
|---|---|---|---|---|
| 1 |
HONEYWELL INTERNATIONAL SRO
Organization address
city: Brno contact info |
CZ (Brno) | coordinator | 0.00 |
| 2 |
ACE ASSOCIATED COMPILER EXPERTS B.V.
Organization address
address: DE RUYTERKADE 113 contact info |
NL (AMSTERDAM) | participant | 0.00 |
| 3 |
Coreworks - Projectos de Circuitos e Sistemas Electronicos S.A.
Organization address
address: Rua Dona Estefania contact info |
PT (Lisboa) | participant | 0.00 |
| 4 |
HONEYWELL EOOD
Organization address
address: BUL HRISTOFOR COLUMB contact info |
BG (SOFIA) | participant | 0.00 |
| 5 |
IMPERIAL COLLEGE OF SCIENCE, TECHNOLOGY AND MEDICINE
Organization address
address: Exhibition Road, South Kensington Campus contact info |
UK (LONDON) | participant | 0.00 |
| 6 |
INESC ID - INSTITUTO DE ENGENHARIA DE SISTEMAS E COMPUTADORES, INVESTIGACAO E DESENVOLVIMENTO EM LISBOA
Organization address
address: Rua Alves Redol contact info |
PT (LISBOA) | participant | 0.00 |
| 7 |
Karlsruher Institut fuer Technologie
Organization address
address: Kaiserstrasse contact info |
DE (Karlsruhe) | participant | 0.00 |
| 8 |
TECHNISCHE UNIVERSITEIT DELFT
Organization address
address: Stevinweg contact info |
NL (DELFT) | participant | 0.00 |
| 9 |
UNIVERSIDADE DO PORTO
Organization address
address: PRACA GOMES TEIXEIRA contact info |
PT (PORTO) | participant | 0.00 |
Mappa
Word cloud
Esplora la "nuvola delle parole (Word Cloud) per avere un'idea di massima del progetto.
Obiettivo del progetto (Objective)
The relentless increase in capacity of Field-Programmable Gate-Arrays (FPGAs) makes them vehicles of choice for both prototypes and final products requiring on-chip multi-core, heterogeneous and reconfigurable systems. Multiple cores can be embedded as hard- or soft-macros, have customizable instruction sets, multiple distributed RAMs and/or configurable interconnections. Their flexibility allows them to achieve orders of magnitude better performance than conventional computing systems via customization. Programming these systems, however, is extremely cumbersome and error-prone and as a result their true potential is only achieved at an unreasonably high effort.nThis project will develop, implement and evaluate a novel compilation and synthesis system approach for FPGA-based platforms. We rely on Aspect-Oriented (AO) Specifications to covey critical domain knowledge to a mapping engine while preserving the advantages of a high-level imperative programming paradigm in early software development and portability. We leverage AO specifications and a set of transformations to generate an intermediate representation using an extensible mapping language (LARA). LARA specifications will allow the exploration of alternative architectures and run-time adaptive strategies enabling the generation of flexible hardware cores that can be easily incorporated into larger multi-core designs. We will evaluate the effectiveness of the proposed approach using partner-provided codes from the domain of audio/video processing and real-time avionics.nWe expect the technology developed here to be integrated by our industrial partners, a leading compilation tool supplier for reconfigurable systems and a worldwide solution supplier of embedded high-performance systems. The academic partners will promote human resources with technical excellence in the area of architectures and software development thus enabling the sustainability of a vibrant information technology European fabric.